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Biegel. Osman, Yu



Analysis of Aluminum-Nitride SOI



ANALYSIS OF ALUMINUM-NITRIDE SOI
FOR HIGH-TEMPERATURE ELECTRONICS

Bryan A. Biegel\ Mohamed A. Osman^ and Zhiping Yu^

Abstract

We use numerical simulation to investigate the high-temperature (up to 500K) operation of SOI MOS-
FETs with Aluminum-Nitride (AIN) buried insulators, rather than the conventional silicon-dioxide (Si02).
Because the thermal conductivity of AIN is about 100 times that of Si02, AIN SOI should greatly reduce
the often severe self-heating problem of conventional SOI, making SOI potentially suitable for high-tem-
perature applications. A detailed electrothermal transport model is used in the simulations, and solved
with a PDE solver called PROPHET. In this work, we compare the performance of AIN-based SOI with
that of Si02-based SOI and conventional (viOSFETs. We find that AIN SOI does indeed remove the self-
heating penalty of SOI. However, several device design trade-offs remain, which our simulations high-
light.

1. Introduction



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I Mercury (448 K1

.Venut (328K)
^^Earth (279K)
.M»n (226K)



T =



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Salum (90K)



Nypluy (SIX)



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Distance from Sun, D (A.U.)



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Silicon-on-insulator (SOI) technology has long promised to enable
electronics operation at higher and lower temperatures than con-
ventional MOSFETs, as well as lower power, smaller device sizes,
and under much higher radiation exposure. Such "extreme" condi-
tions can be common in spacecraft operation, making SOI a very
interesting prospect for future spacecraft electronics. Considering
high temperature requirements in particular, note that beyond the
limitless thermal sink of Earth's atmosphere, spacecraft operation
is a constant battle against temperature extremes to keep the on-
board electronics (for control, communications, sensors, data
storage, etc.) functioning. Figure 1 shows the temperature of a
hypothetical black-body sphere versus distance from the Sun [1],
indicating that high temperatures are inevitable for missions near
the Sun. Even in Earth orbit, typical materials experience temper-
atures up to 400K. U.S. space shuttles leave their cargo bay
doors open for the entire mission in order to vent heat.

In spite of the promise of SOI to enable electronics operation at higher temperatures, the traditional bur-
ied insulator in SOI, silicon-dioxide (Si02), traps heat from the operating device in the operating region
(self-heating), degrading operation and reducing device lifetime (Figure 2b). Thus, in spite of its many
potential advantages over conventional MOSFET electronics (Figure 2a), SOI has not been a serious
contender for spacecraft electronics, which must be absolutely reliable. Recent experiments [2] indicate
that aluminum-nitride (AIN) can be used for the SOI buried insulator. The thermal conductivity of AIN is
about 100 times that of Si02 (136 W/mK versus 1.4 W/mK) and roughly equal to that of silicon itself
(145 W/mK). Thus, using AIN as the buried insulator should essentially eliminate the self-heating pen-
alty of SOI (Figure 2c). AIN SOI might be beneficial not only for general space mission electronics, but
also for high-temperature missions.

To investigate AIN for high-temperature applications, we implemented a detailed electrothermal model of
electronics operation in a PDE solver called PROPHET [3], as described in Section 2 of this paper.



Figure 1. Equilibrium temperature of
black-body sphere vs. distance from
Sun [1]. Temperature increases rapidly
inside orbit of Venus.



1 . NASA Ames Research Center, Mailstop T27A-1 . Moffett Field, CA 94035-1000, biegel@nas.nasa.gov.

2. Washington State University, School of EECS, Pullman, WA 99164-2752, osman@eecs.wsu.edu.

3. Stanford University, CIS-X, Room 335, Stanford, CA 94305-4075, yu@ee.stanford.edu.



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Biegel, Osman, Yu



Analysis of Aluminum-Nitride £01



Figure 2. a) Conventional MOSFET. Sil-
icon-dioxide (SiOs) covers the top of the
wafer as a dielectric between metal inter-
connect lines. Due to the low thermal
conductivity of Si02, the back side of the
integrated circuit is the main sink for heat
generated by device operation, b) Con-
ventional SOI, with Si02 buried insulator.
Heat generated by device operation is
trapped in the active region, c) Proposed
SOI, with AIN buried insulator. The high
thermal conductivity of AIN (roughly
equal to that of silicon) allows heat to
escape to the back-side heat sink.




Silicon
substrata

Back



SHicon
substrate

Back



AIN

Sfllcon ^"**'
substrata

22ZZZ2Eaczzza

Back



Siltcon-Oioxide (ic=1.4 W/mK)
Ql^etal

n-type Silteon {ic=145 W/mK)
p-type Silicon (k=145 W/mK)
Aluminum-Nitride (ic=136 W/mK)



Typical Oimensions:

Top oxide thickness: 10-20 nm
Epi-Silicon layer thkrkness: 0.1-1 |im
Burled insulator thickness: 0.1-1 (im
Silicon substrate thickness: 500 um



Using this model, we performed extensive numerical simulations comparing the high-temperature (up to
500K) operation of conventional MOSFETs, standard SOI (with Si02 buried insulator), and AIN SOI.
Results and discussion of these simulations are presented in Section 3. Section 4 summarizes our con-
clusions from this investigation about the suitability of AIN SO! for high-temperature electronics applica-
tions.

2. Electrothermal Model

The basic model of electronic device operation include the Poisson equation and the electron and hole
continuity equations:



V(eVvj/) = -q(p-n + N)



(1)
(2)

(3)



where ^f is the electrostatic potential, n and p are the electron and hole densities, N is the net fixed
charge (ionized dopant) density, and R is the electron-hole recombination rate. Material and physical
parameters include permittivity e , electron charge q , electron and hole diffusivities D„ and D , and
electron and hole mobilities )x„ and \i . For the recombination rate R , we included only Shockfey-Reed-
Hall recombination -generation, such that:



R =



np - n^



^p{n-ni) + x„{p-ni)



(4)



where n- is the intrinsic carrier concentration of the material, and t^ and x are the electron and hole
recombination lifetimes.

The full electrothermal model adds the thermal generation and diffusion equation to the basic device
equations (1 )-(3):



Cz.37 = V-CKVrj-H/.E



(5)



where T^ is the lattice temperature, J is the total (electron and hole) current density, E is the electro-
static field. Parameters include the specific heat C^ and the thermal conductivity ic of the material.



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Biegel, Osman, Yu



Analysis of Aluminum-Nitnde SOI



V', . -£:



(PDE Model)




PDE Solver
Device Simulator



We used Scharfetter-Gummel discretization [4] for the continuity equations and Maxwell-Boltzmann sta-
tistics for the carrier energy disthbution. [A few test simulations showed that Fermi-Dirac statistics, while
quantitatively more accurate, gave qualitatively identical results in this case.] Our electrothermal model
[5] includes temperature dependencies for all material parameters, including carrier diffusivities, mobili-
ties, and lifetimes, thermal diffusivity, and intrinsic carrier concentration. Simulations reported in this
paper were all for devices operating in the steady-state, so all time derivatives were zero. For this inves-
tigation, we ignored bandgap narrowing and carrier velocity saturation. However, the mobility model
included impurity scattering (doping dependence).

Our electrothermal model was implemented in a partial differ-
ential equation solver called PROPHET [3]. The main feature
of PROPHET is rapid prototyping: the ability to specify and
modify a model at a high level, without ever writing, debug-
ging, or modifying the low-level gridding, discretization, data
handling, and solver code (Figure 3). [Relatively simple oper-
ator routines must sometimes be written, however.] The ability
to modify a model without programming is especially impor-
tant for complex models such as the electrothermal model
used in this work, where investigation of variations of the
model is a significant part of the research. In fact, PROPHET
allows device models, material parameters, and arbitrarily
complex simulation sequences to be defined in the run-time
input script. Other benefits of PROPEHT include the ability to
switch from simple to more complex models in order to con-
centrate computing power on operating regions of interest,
and the ability to gradually phase in numerically problematic
PDE terms in order to achieve solution convergence.

Before describing our simulation results, we need to quantify the device structures investigated. As indi-
cated earlier, every simulation was repeated for three devices: a conventional MOSFET, an Si02 SOI
l\/10SFET, and an AIN SOI MOSFET, as shown In Figure 2. These devices were identical except for the
buried insulator, which was replaced with an equal thickness of silicon for the non-SOl simulations. Two
device sizes were simulated, a long-channel MOSFET and a short-channel MOSFET, the details of
which are given in Table 1 . The source and drain had abrupt box doping profiles at lO^^/cm^ n-type,
extending to the buried insulator in the SOI devices, while the substrate was doped at 5x10^^/cm^ p-
type. Figure 4 shows the assumed device structures as well as the biasing arrangement.

Table 1: MOSFETs Simulated




Figure 3. PDE-solver based electronic
device simulator. Only the system of PDEs
describing the device physics and the device
structure need to be specified. Ideally no
programming is required.



Device Parameter


Long-Channel MOSFET


Short-Channel MOSFET


Channel Length


2500 nm (2.5 nm)


250 nm


Gate oxide thickness


10nm


4 nm


SOI epitaxial silicon (epi-Si) thickness


200 nm


50 nm


SOI epitaxial layer doping


10^^/cm^p-type


10^^/cm^p-type


SOI buried insulator layer thickness


600 nm


200 nm


Total simulation region size


5 ^m X 5 fim


5 |im X 5 |im


Maximum gate/drain voltage


10 V


3V



Finally, some simulation details merit mention. Since the simulation region was only 5 nm square, the
thermal conductivity of the substrate layer was decreased by a factor of 100 to approximate the thermal
resistance of a typical 500 iim thick silicon chip. In initial simulations, we found that the electrothermal
model would not converge without a thermal contact on the top side of the simulation region. We there-
fore made the source and drain thermal (as well as electrical) contacts. Since the top side does pass



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Biegel. Osman. Yu



Analysis of Aluminum-Nitride SOI



a) Conventional MOSFET
I Gate Oram




b) SI02/AIN SOI MOSFET
Gate Dram



ioorce



n5p-teiii|J6Q



SI02/AIN



p-Slllcon
substrate



BacK



^



Figure 4. a) Conventional MOSFET
and b) SOI MOSFET device structures
simulated with biasing set-up. Thermal
contacts are indicated by red lettering.
Two device sizes were simulated: a 2.5
um long-channel device, and a 250 nm
short-channel device. To approximate
a 500 |im thick wafer, the thermal con-
ductivity of the substrate layer was
specified as 0.01 times that of silicon.

some heat to the environment, having these top-side contacts seems reasonable anyway. We note that
these simulations also predict the worst case thermal heating: steady-state. In a real circuit, spatial and
temporal averaging would mitigate this heating extreme. Concerning solution grid sizes, we used about
3600 nodes for the long-channel devices and about 2600 for the short-channel devices. Typical compu-
tation times were 1-2 hours for a 200-point l-V curve simulation on a Sun Ultra II workstation.

3. Results and Discussion

Our investigation of the high-temperature AIN SOI (in comparison to conventional MOSFETs and SOI)
involved the simulation of three operation regimes: OFF (drain leakage), turn-on (subthreshold), and ON
(high-current). Results of these simulations are presented in the following three subsections. Throughout
this section, the conventional MOSFET is indicated as "MOS" in text and with black curves in plots, the
Si02 SOI device is indicated with "SiOg" and red, and the AIN SOI device is indicated with "AIN" arid
green.

3.1. Drain Leakage Simulation

To simulate drain leakage current in the OFF state, gate bias Vq was held at OV, and the drain bias was
ramped up to full (10V for the long channel devices and 3V for the short-channel devices). This operating
regime tests how well the device stays OFF (low drain current), in spite of a large drain bias. For this
operating region, we can make a few predictions:

• Self-heating will be irrelevant, since current (and thus heat generation) will be very low. Thus, the
Si02 and AIN SOI results should be virtually identical.

• Leakage current due to electron-hole pair (EHP) generation in the source and drain p-n junction
depletion regions will be larger in the MOS device, since it has much larger depletion regions.

• Drain-induced barrier lowering (DIBL - drain depletion region extends near that of the source)
should be the same for all the devices of a given size, since the doping profiles from source to
drain are identical. Further, DIBL should be small, since channel doping is high enough to keep the
drain depletion region from extending near the source.

Drain leakage current simulation results are shown in Figure 5. Figure 5a shows the long-channel
results, which are exactly as predicted above. However, Figure 5b for the short-channel device seems to
violate ail of the above predictions - the SiOa and AIN results are widely different, MOS leakage is lower
than SOI, and DIBL is different between the three devices and relatively high for the AIN device. The rea-
son for these results is indicated in Figure 5c, which compares the 2-D potential profiles in the MOS and
AIN devices at 300K and Vd=3V. [The 300K results were compared since they illuminate the cause of
the short-channel results most clearly] The potential plot shows that the barrier to electron flow between
source and drain (indicated by blue), is much higher in the MOS device than in the AIN (and SiOg) SOI
device. A reduced channel barrier and higher leakage current are classic signs of the floating-body prob-
lem of fully-depleted (FD) SOI devices. We can now conclude the following:

• The long-channel SOI devices simulated are partially-depleted (PD). That is, the channel depletion
layer extends only part way through the epi-Si layer towards the buried insulator. As a result, PD
SOI devices operate in many respects like a conventional MOSFET The leakage current predic-
tions above only apply to this type of SOI device.



HiTEC 2000



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Biegel, Osman, Yu



Analysis or Aiuminum-Nitride SOI



a) Long-Channel Leakage Current



b) Short-Channel Leakage Current



E
a.



c


w
3

o

c

o



10




2 4 6 8

Drain Voltage, Vq (V)



Figure 5. Leakage current simulations, a) Long-
channel results. MOS leakage is about 5 times
higher than SOI, due to electron-hole generation in
the much larger pn junction depletion regions, b)
Short-channel results. MOS leakage is now much
lowerthan SOI, and AIN SOI is actually worst, c)
Electrostatic potential plot in channel region of
short-channel MOSFET/AIN SOI at 300K. Blue
represents a potential barrier to electron flow from
source to drain. The MOSFET has a high barrier
(resulting in low OFF-state leakage), while the AIN
has the lowest ban-ier. This shows that the short-
channel SOI devices are fully-depleted.



1 2

Drain Voltage, Vq (V)

c) Electrostatic Potential Contours; 300K
■ Gate




• The epi-Si layer of the short-channel SOI devices is fully-depleted, even at Vg=OV. That means
that the drain depletion region is able to punch through to affect the source-channel energy barrier,
with the resulting observed DIBL. The lowest barrier, and most of the leakage current flow, are at
the epi-Si/buried insulator interface, as indicated in Figure 5c.

• The higher leakage current of the AIN device results from a lower barrier to electron flow compared
to that in the Si02 SOI device. The cause of the difference will be made clear in Section 3.2. We
will evaluate at the end of Section 3.3 whether the leakage current of the AIN device at 500K is
high enough to threaten proper operation of the device.

The results in this section show that there are potential advantages and disadvantages of fully-depleted
SOI. However, there are advantages of properly-designed FD SOI over PD SOI, especially for sub-
micron devices [6]. We have not attempted to in this work to optimize the design of either the long-chan-
nel PD SOI device or the short-channel FD SOI device.

3.2. Subthreshold Simulation

The subthreshold operating regime is simulated by ramping the gate voltage while holding the drain bias
at a low value. For both long-channel and short-channel devices, we used Vd=0.1 V. This operating
regime tests how quickly the increasing gate bias turns on the device (increases drain current). Again,
we make a few predictions of the expected device operation, although we now know that the operation of
the FD short-channel SOI devices may be more complicated.

• Once again, self-heating will be irrelevant, in this case because drain bias (and thus heat genera-
tion) is small. Thus, the Si02 and AIN SOI results should be virtually identical.

• For the PD SOI, the operation should be virtually identical to that of the MOSFET, since the buried
insulator does not affect the activity in the surface inversion layer.



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Biegel. Osman. Yu



..iiV^I-



:r A,:.minum-NitrJde SOI



• For the FD SOI, it is difficult to predict the effect of the buried insulator on the electron inversion
layer as the gate bias increases.

Subthreshold current simulation results are shown in Figure 6. Once again, the results for the long-chan-
nel devices are as predicted. Note that the higher current of the MOS device near Vq^OV is due to its higher
leakage current, as found in Section 3.1. Once again, the short-channel results are surprising. This time, rather
than both SOI devices being worse than MOS, one is worse (AIN SOI has a /7/g/7er subthreshold slope), and the
other is better (SiOa SOI has a tower subthreshold slope). These results are consistent over the full simulated tem-
perature range from 300K to 500K.



a) Long-Channel Subthreshold Current



b) Short-Channel Subthreshold Current



(Vd=0.1V)



(STS: Subthreshold Slope)




nv/decade
f2mV/decade
aOmV/decade



-MOS
-SiOa
-AIN



E



IQ-J _



-- 10'^



t
3

o

c

2

a



10-" -



10



1-12



(Vo=o.iv)


^




^%^\,^^ _^ /


-MOS

- SiOj (best)

- AIN (worst)








-,^^/


300K: 70±3mV/dec
400K: 98±5mV/dec
500 K: 1 30±7 mV/dec




1



Gate Voltage, Vq (V)

Figure 6. Subthreshold current simulations, a)
Long-channel results. All devices have virtually
identical subthreshold characteristics, b) Short-
channel results. The subthreshold slope (STS) of
SiOa SOI Is better than MOS, while that of AIN SOI
is slightly worse. Higher SOI currents reflect the FD
SOI floating-body effect, c) Change in electron
density for all 250nm devices at 500K near Vg=OV.
This shows that the Si02 SOI has lower STS than
MOS because the Si02 SOI inversion charge is
confined to a thinner region. Conversely, AIN SOI
has a higher STS because a significant electron
charge Is Induced below the buried insulator



0.5
Gate Voltage, Vq (V)



c) Change in Electron Density: 500K, O^V-OV






To clarify the cause of these short-channel device results, note the in the subthreshold region, we are
concerned about how effectively an increasing gate bias turns on the drain current. With drain bias fixed,
the only thing the gate bias can do is increase the channel inversion charge. Thus, the definitive reason
for differing subthreshold effects can be obtained by comparing where and how much the electron den-
sity increases in the channel for a given gate bias change. This is plotted in Figure 6c. Here we see that
the Si02 SOI device improves on the MOS device because its inversion charge increase is confined to
the epi-Si layer (with a small electron build-up below the buried insulator), while the fvlOS device inver-
sion layer extends deeper into the substrate. The further from the gate that the inversion charge is, the
less inversion charge will be needed to accommodate an increase in gate bias. In contrast, in the AIN
SOI device, a significant portion of the gate bias is accommodated by charge beneath the buried insula-
tor. Thus, there is less inversion charge in the epi-Si active layer to contribute to drain current.

What is the reason for the Si02/AIN SOI difference, when their device structures and doping densities
are identical? As indicated in Figure 6c, the crucial difference, which manifests itself both in subthreshold
and in the leakage current simulations of Figure 5b, is a result of the different dielectric constants of the
two buried insulators. In particular, the higher permittivity of AIN as compared to Si02 means that electric
fields penetrate the AIN layer with much less attenuation than for the same thickness of Si02. Thus,



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Bierel Osman Yu Analysis of Aluminum-Nitnde SOI

more of any change gate potential is dropped in the substrate in AIN SOI than in SiOs SOI, with corre-
spondingly less change in potential in the epi-Si layer where it would increase inversion charge. Alterna-
tively, consider the SOI structure is as two parallel plate capacitors in series. To maximize the
effectiveness of the gate bias to increase electron density in the epi-Si layer, the gate oxide capacitance
should be much larger than the buried insulator capacitance. Since parallel plate capacitance is propor-
tional to the dielectric constant of the intervening material, the capacitance of the AIN capacitor is
greater than that of the Si02 buried insulator capacitor. The apparent solution for improving the perfor-
mance of AIN SOI is now clear - increase the thickness of the AIN layer. This decreases the capacitance
of this layer, forcing more of the gate potential to be felt in the epi-Si layer.

3.3. High Current Simulation

For the n-channel MOSFETs used in this study, high-current operation (device ON) is achieved with
large positive gate and drain biases. For this simulation, the gate bias was held at its full ON value, while
the drain bias was ramped from OV to full bias. The predictions for device operation in this case are
straight-fonward:

• Since both current and drain bias are high, thermal generation will be large in the device active
layer. Thus, Si02 SOI should show significant self-heating effects, including high channel tempera-
ture, degraded current and mobility, and strong negative differential conductance (NDC).

• fvlOS and AIN SOI should have much lower self-heating effects, but similar to each other. They
may still display moderate NDC.

Figure 7 shows the high-current simulation results. As shown in Figures 7a and 7b, both long-channel
and short-channel simulation results were as expected, since self-heating is the dominant effect in these
simulations. Note that self-heating was so strong in the Si02 SOI device that all but one of the simula-
tions did not complete the current-voltage trace to full drain bias - NDC effects rendered the system of
equations non-convergent. To demonstrate self-heating more clearly. Figures 7c, 7d, and 7e show, for
the long-channel devices at Tenv=500K and 7^=1 OV, the channel mobility, vertical temperature profile
through the channel center, and a 2-D temperature plot of the channel region. Each of these show dra-
matically how strong self-heating effects are in the SIO2 SOI device. The self-heating difference was
even more dramatic in the short-channel devices: peak temperature of almost 1000K for Si02 SOI, but
only device, while the maximum was under 630K for AIN. The Si02 device would surely melt itself before
reaching such high temperatures. On the other hand, it is quite conceivable to use materials suitable for
integrated circuit operation with internal temperatures just above 600K, as in the AIN devices operating
in a 500K environment.

Before concluding, we return to a question raised in Section 3.1 : Is the short-channel, AIN leakage cur-
rent at 500K too high? The answer is yes if leakage is an appreciable fraction of the full ON current.
Comparing the appropriate curves in Figures 5b and 7b, we see that even the highest leakage current is
still almost 4 orders of magnitude smaller than the ON current, so the high AIN leakage is not a practical
concern. We note that the leakage current is also too small to cause any appreciable self-heating.

4. Conclusions

With detailed electrothermal simulations, we showed the significant self-heating effects of conventional
SOI, including high channel temperature, degraded current and mobility and strong negative differential
conductance (NDC). We showed that AIN SOI removes the self-heating penalty of SOI, allowing AIN SOI
to function in a 500K environment. While partially-depleted SOI has lower drain leakage current than
conventional MOSFETs, fully-depleted (FD) SOI has advantages for short-channel devices. However,
FD SOI requires care is choosing the epitaxial silicon layer thickness and doping as well as the buried
insulator thickness to maintain drain leakage at acceptable levels and to optimize turn-on characteristics.
AIN-based SOI requires additional attention, due to the higher dielectric constant of this material com-
pared to Si02. We expect that a thicker buried insulator, as compared to Si02-based SOI, will allow AIN
SOI to maintain good operation in high-temperature applications and in general.



HiTEC2000 7 June 1 1-15. 2000



Biegel. Osman. Yu



Analysis cf Aluminum-Nitricle SO!



a) Long-Channel High-Bias Currant




b) Short-Channel MIgh-Bias Current



M

«^

E
_o

c
a.

"S
o
S
c
2

I

lU



800



600



400



200 -



-2.5



2 4 6 8 10

Drain Voltage, Vo (V)

c) Long-Channel 500K Mobility Profile






^i, = /(^. TO


-MOS
-SiOz
-AIN






300K






400K






500K


^^=^




Source ,




Drain



900



I 2 3

Drain Voltage, Vq (V)

d) Long-Channel 500K Temperature Profile



-1.25 1.25

Position Along Channel (jim)



2.5




Figure 7. High-bias simulations, a) Long-channel
results, showing a significant self-heating degrada-
tion in SiOg SOI, which is totally absent in AIN SOI.
However, self-heating causes negative differential
conductance (NDC) in all three devices, b) Short-
channel results (similar to the long-channel). The del-
eterious effects of self-heating in Si02 SOI increase
somewhat with temperature. Other long-channel,
500K results showing the significant increase in lat-
tice temperature in Si02 SOI due to self-heating: c)
mobility profile along the top surface, showing signifi-
cant mobility degradation in SiOa SOI; d) vertical
temperature profile with 350K greater temperature
rise in SiOg SOI; and e) 2-D temperature plot.



e) Long-Channel 500K Temperature Contours



Source



Chann»l




SSEIl




References

[1] Alan C. Tribble, The Space Environment: Implications for Spacecraft Design, Princeton University
Press, Princeton, NJ, 1995.

[2] S. Bengtsson, M. Bergh, M. Choumas, C. Olesen, and K.O. Jeppson, "Application of Aluminum
Nitride Films Deposited by Reactive Sputtering to Silicon-On-tnsulator Materials", Japanese Journal
of Applied Physics, Vol. 35, Part I, No. 8, p. 4175 (1996).

[3] PROPHET home page: http://www.tcad-stanford.edu/~prophet.

[4] D.L Scharfetter and H.K. Gummel, "Large-Signal Analysis of a Silicon Read Diode Oscillator", IEEE
Transactions on Electron Devices, Vol. Ed-16, p. 64 (1969).

[5] Z. Yu, D. Yergeau, R.W. Dutton, S. Nakagawa, N. Chang, S. Lin, and W. Xie, "Full chip thermal simu-
lation," International Symposium of Quality Electronic Design, p. 145, Santa Clara, CA, March, 2000.

[6] J.Y. Choi and J.G. Fossum, "Analysis and Control of Floating-Body Bipolar Effects in Fully-Depleted
Submicrometer SOI MOSFET's", IEEE Transactions on Electron Devices, Vol. 38(6), p. 1384 (1991).



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